Memory units are very common in many different types of products. All memory units are programmable but the types of memory units differ in whether or not and how they are erased. Read only memory (ROM) units are not erasable and require replacement if the information programmed therein must be changed. Erasable programmable, read only memory (EPROM) units use electrical signals to program them but require ultraviolet light to erase the entire chip at once. Electrically erasable programmable, read only memory (EEPROM) units and FLASH EEPROM units use electrical signals for erasing and for programming. Thus, a single bit or a single word can be changed if desired.
Included in the term "memory units" are programmable logic devices (PLDs) which, instead of storing data as do memory units, store logical equations. A PLD can be based on any of the memory unit types.
To reprogram a programmable memory unit, the unit must be placed into a programming device which erases the unit in the appropriate manner and then electrically programs the unit. For memory units formed in a chip which is connected to a circuit board via a socket, this is not a problem since the units are typically removable from the socket.
However, those units which are directly soldered to the circuit board and those which are formed within a multifunction chip cannot be removed to the programming device. These units can be operated on (i.e. read, programmed, erased, verified, etc.) via a parallel port.
In-system programming (ISP) provides a method of operating on an on-chip memory unit, or any non-removable memory unit. IEEE Standard 1149.1 defines a test access port, known as a "JTAG port", through which in-system programming occurs using a serial channel. FIGS. 1A and 1B, to which reference is now made, illustrate the JTAG port and its operation. FIG. 1A illustrates a personal computer (PC) 10 having a parallel port 11 which controls a chip 12 having a JTAG port 14 while FIG. 1B illustrates the method of operation, in the form of a state machine, through the JTAG port 14.
In order to operate with a JTAG port, the chip 12 must also have a JTAG controller 16 which converts the serial data transmitted through the port to the parallel format needed for accessing the memory unit, labeled 18, via a parallel bus 20. The bus can either be a single bus for data and address signals or two busses, one for data signals and one for address signals. In addition, the JTAG controller 16 decodes the instructions sent to into control signals for controlling the operation of the memory unit 18. These control signals are provided to the memory unit 18 via a control bus 29.
The JTAG port 14 has four pins, one each for the clock signal TCK, a control signal TMS, a data in signal TDI and a data out signal TDO, and the JTAG controller 16 includes a state machine 22, a data shift register 24, an instruction shift register 27 and an instruction decoder 28.
The data in signal TDI is a serial presentation of the data and address information to be provided to the memory unit 18 as well as of the instructions to the memory unit 18. The data and address information is provided to data shift register 24 which shifts in the serial data provided by signal TDI. The data shift register 24 thus has enough storage units to hold both data (typically of 8 bits) and address (typically of 16 bits). The instructions are provided to the instruction shift register 27.
Via parallel port 11, the PC 10 provides the clock signal TCK and the control signal TMS to the state machine 22 which, in turn, controls the operation of the JTAG controller 16. Accordingly, the PC 10 also drives the data in signal TDI and monitors the data out signal TDO. The various instructions forming the control signal TMS are indicated in FIG. 1B. As the operation of the JTAG controller 16 is fully defined in the IEEE standard 1149.1, the following discussion will only highlight portions of the operation.
Initially, whatever information is on bus 20 is captured (state 32) and placed into data shift register 24. The data and address information of data in signal TDI is then shifted (state 34) into data shift register 24, causing the captured data to be shifted out, as data out signal TDO. Once a full set of data and address information has been shifted into data shift register 24, the state machine 22 indicates (state 42) to data shift register 24 to provide the data to parallel bus 20. State machine 22 then indicates (state 44) to the instruction decoder 28 to provide the instructions, via control bus 29, to memory unit 18 to run the desired operation (reading, programming, erasure, verification, etc.) for the address.
PC 10 then waits a predetermined length of time T, as defined for each type of operation, before transmitting the next series of data and address bits. The length of time is set to ensure that the desired operation finishes before the next set of data is shifted in.
The timing is shown in FIG. 1C for two bytes, labeled BYTE 0 and BYTE 1. The shifting operation for BYTE 0, as indicated by the data in TDI signal, occurs first, during which the 24 data and address bits are shifted into data shift register 24 and 24 blank bits are shifted out to data out signal TDO. Once the data has been shifted into register 24, the state machine 22 moves to the UPDATE state 42 after which the state machine moves to the run-test/idle state 44 in which an R-T-I pulse 45 is generated. The memory unit 18 then performs the operation, as indicated by the OPERATION signal. As noted, the OPERATION signal returns to its non-active state well within the period of length T allotted to it. The process repeats itself with the next shift operation, for BYTE 1, during which the data of BYTE 0 is shifted out to data out signal TDO.
It will be appreciated that using the JTAG port 14 to operate on a memory unit is time consuming due to the serial transfer of the data and the long wait until the operation has finished for each byte.